Intel says its chip stacking will usher a ‘new era’ of semiconductors

23 Aug 2022

Image: © Chromawave/

Intel’s CEO said the company aims to move from 100bn transistors to 1trn by 2030 through various innovations such as ‘chiplet’ technology.

Intel has showcased new technical details about its architectural and packaging innovations, which it claims will help meet the world’s growing compute demands, bring about a “new era” in chipmaking and propel Moore’s Law forward.

The chipmaker highlighted its plans at Hot Chips, a major semiconductor industry event. Intel had its first CEO keynote at the event since 1995, where Pat Gelsinger said the company has an “aspiration to move from 100bn transistors on a package today to 1trn by 2030”.

One of the key pieces of architecture that Intel previewed was its latest batch of processors that use “tile-based chip designs” for more efficient manufacturing, power and performance.

The Meteor Lake, Arrow Lake and Lunar Lake processors utilise “chiplet” architecture, which is a method of using multiple, smaller modules to build a single larger processor. By using this modular approach, Intel believes it can boost the power of processors.

Intel said its latest processors feature CPU, GPU, system-on-a-chip (SoC) and I/O tiles stacked in 3D configurations using its Foveros interconnect technology.

When Intel unveiled Foveros in 2018, it claimed this manufacturing technology would help boost the performance of a variety of chips, from core processors to AI-specific chips.

The use of chiplets also offers a form of manufacturing flexibility. Intel said an open specification allows chiplets designed and manufactured on different process technologies by different vendors to work together when integrated with advanced packaging technologies.

According to CNET, three of Meteor Lake’s four data-processing chiplets are built by TSMC, which could help Intel deal with its manufacturing problems. Supply chain issues and the global chip crunch have taken their toll on the semiconductor giant, which gave a gloomy outlook in its first-quarter earnings results.

Intel shared details of its Xeon D-2700 and 1700 series processors, which the chipmaker said are also examples of tile-based design. These chips are designed for 5G, IoT, enterprise and cloud applications, with considerations to the power and space constraints that exist in many real-world scenarios.

Intel also revealed its new GPU known as Ponte Vecchio, which it designed to meet compute density across high-performance computing and AI supercomputing workloads.

The chipmaker said this GPU utilises Intel’s open software model, using OneAPI to simplify API abstractions and cross-architecture programming.

Moore’s Law

In 1965, Intel co-founder Gordon E Moore made a prediction that the power of chips would double roughly every year. This idea became known as Moore’s Law and was revised in 1975 to change it to a doubling every two years.

The law was followed by the industry for decades, until 2016 when claims were made that the idea was no longer feasible. An article in Nature claimed semiconductors had reached a developmental point where a doubling of capacity was proving almost impossible.

However, the utilisation of chiplets harks back to Moore’s theory, as he made a prediction for this form of technology in his original paper, titled ‘Cramming more components onto integrated circuits’.

“It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected,” Moore wrote at the time.

According to a recent article by executive vice-president Dr Ann Kelleher, Intel believes 3D stacking technologies will give designers the tools to further increase the number of transistors per device and will contribute to the scaling needed for Moore’s Law.

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Leigh Mc Gowran is a journalist with Silicon Republic